1. Field of the Invention
The present invention relates to a test facilitating circuit provided in an LSI system, and particularly to construction of a test facilitating circuit provided in an LSI system so constructed that a plurality of master modules can access a plurality of slave modules.
2. Description of the Prior Art
When an operational test of an LSI system constructed so that a plurality of master modules, for example, Central Processing Units (CPU) or Direct Access Memory Controllers (DMAC) are connected with a common bus to access a plurality of slave modules is carried out, it is necessary to set or read test data to each slave module (for example, a RAM as a memory element) which is dependent on each of the master modules.
Conventionally, a parallel scan method or a serial scan method is used as a method of testability on logic circuits.
Generally, in the parallel scan method, addresses of respective modules, for example memory circuits, in a logic circuit are selected as test data so as to carry out the operational test of the logic circuits.
However, in such a method, a test facilitating circuit (for example, address buses, data buses, and selectors only used for the operational tests) must be provided to each of the modules. The LSI scale of the system therefore is inevitably increased.
On the other hand, the serial scan method is used for operational tests of, for example, F/F and the like in the master modules. In this method, the number of circuits for the operational tests is smaller than that of the parallel scan method, however, the test time is longer than that of the other method. This problem increases as the integration degree of LSI becomes large.
In efficiency of the test time, the parallel scan method is superior to the serial scan method. However, the parallel scan method is inferior to the serial scan method in that the former method requires a larger scale test circuit than that of the latter.